InAs gate-all-around nanowire MOSFETs by top-down approach

Abstract

InAs gate-all-around (GAA) nanowire MOSFETs are experimentally demonstrated for the first time by a top-down approach <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[1-3]</sup> . Thanks to the well-controlled nanowire release process and the novel ALD high-k/metal gate stack process, InAs nFETs with channel length (L <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ch</inf> ) ranging from 380 to 20 nm and nanowire width (W <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">NW</inf> ) from 60 to 20 nm are achieved. With an EOT of 3.9 nm, high drain current of 4.3 A/mm at V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</inf> = V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</inf> = 2 V and maximum transconductance (g <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</inf> ) of 1.6 S/mm at V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</inf> = 1 V are obtained in a device with W <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">NW</inf> = 20 nm and L <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ch</inf> = 180 nm, normalized by the perimeter of the nanowires. A detailed scalability study (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</inf> , g <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</inf> , I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</inf> vs. L <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ch</inf> ) was carried out. The devices in this study show strong dependence on the nanowire width and smaller nanowire size offers much enhanced electrical performance and better immunity from the short channel effects (SCEs).