In Situ SRAM Static Stability Estimation in 65-nm CMOS

Abstract

This paper presents a method to rapidly estimate the read and write stability of cells within an SRAM array without modifying the cell structure. The approach measures the read or write bit-line current for a few supply levels and apply the measurements to an estimation function to determine the read stability and write ability of the cell. The estimation function can be determined by regression using stability measurements for a subset of the memory. A low-area sensing circuit and an on-chip time-based ADC measures the bit-line current. The step size of the supply voltage for estimating the stability is 100 mV and for determining the estimation function is 25 mV with an accuracy of ±1 mV. Measurement data show that the estimation error sigma is as small as 4.77% for the read stability and 1.3% for the write ability estimation. The validity of the approach is verified in measurements across multiple dice from a test chip fabricated in a 65-nm CMOS technology.