In-Memory modelling and simulations

Abstract

A mechanism for modeling faults as addresses on smart data structures is proposed, which excludes the algorithm for modeling input test sets to obtain a test map of logical functionality. Smart data structures are represented by a logical vector and its derivatives in the form of truth tables and matrices. The test map is a matrix whose coordinates are defined by the combinations of all logical faults that are tested on the binary sets of the exhaustive test. The construction of the test map is focused on the architecture of in- memory computing based on read-write transactions, which makes the simulation mechanism economical in terms of simulation time and energy consumption due to the absence of a central processor. A logical vector as a single component of input data does not require synthesis into a technologically permitted structure of elements. Synthesis of smart data structures based on four matrix operations creates a fault test map like addresses for any logic. The proposed mechanism is focused on the service of SoC IP-cores under the control of the IEEE 1500 standard. The proposed mechanism has no analogues in the design and test industry in terms of simplicity and predictability of data structure sizes and the absence of a test set modeling algorithm.