Abstract

Channel codes, such as low-density parity-check (LDPC) codes, may be employed in wireless communication schemes for correcting transmission errors. This tolerance to channel-induced transmission errors allows the communication schemes to achieve higher transmission throughputs, at the cost of requiring additional processing for performing LDPC decoding. However, this LDPC decoding operation is associated with a potentially inadequate processing throughput, which may constrain the attainable transmission throughput. In order to increase the processing throughput, the clock period may be reduced, albeit this is at the cost of potentially introducing timing errors. Previous research efforts have considered a paucity of solutions for mitigating the occurrence of timing errors in channel decoders, by employing additional circuitry for detecting and correcting these overclocking-induced timing errors. Against this background, in this paper, we demonstrate that stochastic LDPC decoders (LDPC-SDs) are capable of exploiting their inherent error correction capability for correcting not only transmission errors, but also timing errors, even without the requirement for additional circuitry. Motivated by this, we provide the first comprehensive tutorial on LDPC-SDs. We also propose a novel design flow for timing-error-tolerant LDPC decoders. We use this to develop a timing error model for LDPC-SDs and investigate how their overall error correction performance is affected by overclocking. Drawing upon our findings, we propose a modified LDPC-SD, having an improved timing error tolerance. In a particular practical scenario, this modification eliminates approximately 1-dB performance degradation that is suffered by an overclocked LDPC-SD without our modification, enabling the processing throughput to be increased by up to 69.4%, which is achieved without compromising the error correction capability or processing energy consumption of the LDPC-SD.

Highlights

  • Low-Density Parity-Check (LDPC) codes [1] are employed in wireless communication systems such as IEEE 802.11n/ac (WiFi) and IEEE 802.16e (WiMAX) [2] for correcting transmission errors, which are induced by channel effects such as noise, fading, interference and dispersion

  • We use simulations at the algorithm level to investigate the decoders’ Bit Error Ratio (BER) performance, but we incorporate a model of the causes and effects of timing errors, which is parametrized by characteristics obtained from the lower design levels of Fig. 13

  • The most realistic experimental results can only be obtained by taking measurements from a fabricated Application-Specific Integrated Circuit (ASIC), this implies a huge amount of design time, effort and financial investment, which may not deliver the desired performance as described above

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Summary

A Tutorial and a Design Example

Abstract—Channel codes such as Low-Density Parity-Check (LDPC) codes may be employed in wireless communication schemes for correcting transmission errors This tolerance to channel-induced transmission errors allows the communication schemes to achieve higher transmission throughputs, at the cost of requiring additional processing for performing LDPC decoding. Previous research efforts have considered a paucity of solutions for mitigating the occurrence of timing errors in channel decoders, by employing additional circuitry for detecting and correcting these overclocking-induced timing errors. Against this background, in this paper we demonstrate that stochastic LDPC decoders (LDPC-SDs) are capable of exploiting their inherent error correction capability for correcting transmission errors, and timing errors, even without the requirement for additional circuitry. In a particular practical scenario, this modification eliminates the approximately 1 dB performance degradation that is suffered by an overclocked LDPC-SD without our modification, enabling the processing throughput to be increased by up to 69.4%, which is achieved without compromising the error correction capability or processing energy consumption of the LDPC-SD

INTRODUCTION
BACKGROUND
Literature Review
LDPC Decoding Algorithm and Fully Parallel Implementation
Stochastic Computation in LDPC Decoders
MOTIVATION AND DESIGN FLOW
Stochastic
BER Results measurement
OVERCLOCKING-INDUCED TIMING ERROR ANALYSIS
Nominal Signal Propagation Delays of Stochastic LDPC Decoders
Propagation Delay Fluctuation
Effects of timing errors in Stochastic LDPC Decoders
Validation in SPICE
MODIFIED STOCHASTIC LDPC DECODER
Modified EM
Overclocking-Induced Timing Error Analysis
SIMULATION RESULTS AND DISCUSSIONS
Inherent Timing Error Tolerance
Improved Timing Error Tolerance
Processing Throughput
Processing Energy Consumption
CONCLUSIONS
New York
Full Text
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