Abstract

Compact model of single-walled semiconducting carbon nanotube field-effect transistors (CNTFETs) implementing the calculation of energy conduction subband minima under VHDLAMS simulator is used to explore the high-frequency performance potential of CNTFET. The cutoff frequency expected for a MOSFET-like CNTFET is well below the performance limit, due to the large parasitic capacitance between electrodes. We show that using an array of parallel nanotubes as the transistor channel combined in a finger geometry to produce a single transistor significantly reduces the parasitic capacitance per tube and, thereby, improves high-frequency performance.

Highlights

  • Carbon nanotubes belong to the fullerenes family and are sheets of graphite rolled in the shape of a tube

  • In order to make a direct measurement of a recognized high-frequency figure of merit, such as fT small signal S-parameter measurements were achieved by a newly developed multiple-channel carbon nanotube fieldeffect transistors (CNTFETs) structure whose output impedance is much lower than the usual single-channel CNTFET and a deembedding scheme that removes existing errors in measured S-parameters [9]

  • Using an array of parallel nanotubes as the transistor channel combined in a finger geometry to produce a single transistor significantly reduces the parasitic capacitance per tube and, thereby, improves high-frequency performance

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Summary

Introduction

Carbon nanotubes belong to the fullerenes family and are sheets of graphite rolled in the shape of a tube. The CNTFET can be characterized by high carrier mobility, low leakage current, important on state current relatively to the applied voltages, and low inverse subthreshold slope. These properties allow us to consider the design of high-speed and high-performance electronic circuits. We use compact model, in a quasi-static approach simulations to examine the high-frequency performance potential for a state-of-the-art CNTFET. Using an array of parallel nanotubes as the transistor channel combined in a finger geometry to produce a single transistor significantly reduces the parasitic capacitance per tube and, thereby, improves high-frequency performance.

Approach
Quasistatic Approach and Results of Simulation
Multifinger Multitube Field-Effect Transistors
G Figure 10
Conclusions
Full Text
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