Abstract
This article introduces a high-performance packet filter design in which we propose the partial parallel range check (PPRC) technique for speeding up port range check. Unlike the conventional serial design that uses cascading cells to perform the serial check, PPRC divides the single path into several segments. All PPRC segments perform the range compare simultaneously, that is, parallel check, and then the results of each segment are serialized to generate the final check result. Besides theoretical analyses, we also use UMC 90nm CMOS process to implement the PPRC design and verify its effect on the check performance. Compared to state-of-the-art range check techniques, the results show that the PPRC design with the best configuration can improve check performance by 28%, at least. In addition, the PPRC design is more stable and energy efficient than related designs, even though it requires more transistors to implement the peripheral circuitry. The range of energy improvement achieved by the PPRC design is about 35%--70%.
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