A Novel 19.6 GHz, High Speed and Low Power Dual Modulus 2/3 Design based on Implication Logic Cells in 130nm CMOS Technology

Abstract

In this paper, we describe the merging technique and non-traditional logics for design of a divide - (÷) by-2/3 design. The proposed circuit of design consumes a smaller amount of power than true single - phase clock (TSPC), Current - mode logic (CML) logic styles and operates faster than enhanced TSPC(ETSPC) designs. By theoretical analysis, one can conclude that the switching power and propagation delay of the proposed circuit is less than that of conventional ÷ - by - 2/3 prescaler. The Power consumption of proposed circuit is reduced by 39% as compared with the conventional design. The design is realised in 130 nm CMOS process at power consumption of 8μW under 0.8V of a supply voltage, andthe maximum working frequency reaches up to 19.6 GHz.