Improving the division instruction of application-specific RISCs

Abstract

This paper presents the development and application of a signed radix-4 division algorithm to a RISC architecture, where the internal ALU Manchester Carry adder is used to maintain the partial remainder in irredundant form. There are division algorithms which are faster than the one described in this paper, however, they usually make use of a redundant representation of the partial remainder and require carry-save adders which are not normally used in the integer execution unit of RISCs. The method presented in this contribution employs 3x divisor multiples and uses a reduced next divisor multiple estimate table which is implemented by a small and fast logic. Alternative radix-4 schemes with quotient digits {-2,-1,0,1,2} require large and slow PLAs for quotient digit generation. Additionally, there is no need for positive and negative quotient registers because quotient bits are generated on-the-fly by a small-sized logic, concurrently with partial remainder formation. This method also deals directly with signed two's complement numbers, eliminating the need for additional instructions for sign conversion. The application of this radix-4 division algorithm provides a two-bits-at-a-time division instruction, instead of the traditional single bit approach used in some RISCs. The speedup achieved can be very important in many numeric intensive applications, in which the use of floating-point units is not essential.