A radix-2 general division algorithm with carry-free scheme and the divider implementation

Abstract

A carry-free subtractive division algorithm is proposed in this paper. In the conventional subtractive divider, an adder is used to find both the quotient bit and partial remainder. The carry is usually generated in the adder, and therefore the carry propagation delay is the bottleneck of the conventional subtractive divider. In this paper, the signed bit representation is applied to the quotient bit and partial remainder. A very easy scheme is used to decide the quotient bit, and the new partial remainder is found by a table look-up like method. This new approach is carry propagation free and thus fast operation can be expected. Based on this algorithm a prototype of a 32-b/32-b divider is designed in Verilog HDL, and simulation shows that this algorithm is feasible to a real divider.