Abstract
Contemporary digital systems include many varying sequential blocks. In the article, we discuss a case when Mealy finite state machines (FSMs) describe the behavior of sequential blocks. In many cases, the performance is the most important characteristic of an FSM circuit. In the article, we propose a method which allows increasing the operating frequency of multi-level look-up table (LUT)-based Mealy FSMs. The main idea of the proposed approach is to use together two methods of structural decomposition. They are: (1) the known method of transformation of codes of collections of outputs into FSM state codes and (2) a new method of extension of state codes. The proposed approach allows producing FPGA-based FSMs having three levels of logic combined through the system of regular interconnections. Each function for every level of logic was implemented using a single LUT. An example of the synthesis of Mealy FSM with the proposed architecture is shown. The effectiveness of the proposed method was confirmed by the results of experimental studies based on standard benchmark FSMs. The research results show that FSM circuits based on the proposed approach have a higher operating frequency than can be obtained using other investigated methods. The maximum operating frequency is improved by an average of 3.18 to 12.57 percent. These improvements are accompanied by a small growth of LUT count.
Highlights
Digital systems are widely used in our daily life [1]
We propose a method for the solution of this problem in the case in which circuits of Mealy finite state machines (FSMs) are implemented using field programmable gate arrays (FPGAs)
Since the Xilinx is the largest manufacturer of FPGA chips [13], we focus our research on its solutions
Summary
Digital systems are widely used in our daily life [1]. They can be viewed as combinations of various sequential and combinational blocks [2,3]. Our current article is devoted to synthesis of multi-level LUT-based circuits of Mealy FSMs obtained using the methods of structural decomposition. The main goal of our article is to increase the operating frequency of LUT-based Mealy FSM circuits To achieve this goal, we try to reduce the number of levels of LUTs between the FSM inputs and FSM outputs. The main contribution of this paper is a novel design method aimed at increasing the operating frequency of two-level LUT-based Mealy FSMs. The main idea of the proposed approach is to use together two methods of structural decomposition. There are exactly three levels of LUTs in the part of FSM circuit implementing the system of outputs It produces FSM circuits having regular system of interconnections, where each level of logic has its unique systems of inputs and outputs.
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