Abstract
This brief presents a technique for improving the power-delay performance of subthreshold source-coupled logic (SCL) circuits. Based on the proposed approach, a source-follower buffer stage is used at the output of each SCL stage. Analytical results confirmed by measurements in 0.18-mum CMOS technology show an improvement by a factor of as high as 2.4 in power-delay product (PDP). It is also shown that the proposed technique can be used for implementing subthreshold ultra-low power SCL logic gates with a better power and area efficiency, compared to the traditional SCL subthreshold circuits. An optimized approach is proposed to improve the power efficiency of ultra-low power STSCL library cells.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: IEEE Transactions on Circuits and Systems II: Express Briefs
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
