Improving Integrated Circuit Performance Through the Application of Hardness-by-Design Methodology

Abstract

Increased space system performance is enabled by access to high-performance, low-power radiation-hardened microelectronic components. While high performance can be achieved using commercial CMOS foundries, it is necessary to mitigate radiation effects. This paper describes approaches to fabricating radiation-hardened components at commercial CMOS foundries by the application of novel design techniques at the transistor level, the cell level, and at the system level. This approach is referred to as hardness-by-design. In addition, trends in the intrinsic radiation hardness of commercial CMOS processes will be discussed.