Abstract
With ever-increasing wireless network demands, low-complexity reconfigurable filter design is expected to continue to require research attention. Extracting and reconfiguring channels of choice from multi-standard receivers using a generalized discrete Fourier transform filter bank (GDFT-FB) is computationally intensive. In this work, a lower compexity algorithm is written for this transform. The design employs two different approaches: hybridization of the generalized discrete Fourier transform filter bank with frequency response masking and coefficient decimation method 1; and the improvement and implementation of the hybrid generalized discrete Fourier transform using a parallel distributed arithmetic-based residual number system (PDA-RNS) filter. The design is evaluated using MATLAB 2020a. Synthesis of area, resource utilization, delay, and power consumption was done on a Quartus 11 Altera 90 using the very high-speed integrated circuits (VHSIC) hardware description language. During MATLAB simulations, the proposed HGDFT algorithm attained a 66% reduction, in terms of number of multipliers, compared with existing algorithms. From co-simulation on the Quartus 11 Altera 90, optimization of the filter with PDA-RNS resulted in a 77% reduction in the number of occupied lookup table (LUT) slices, an 83% reduction in power consumption, and an 11% reduction in execution time, when compared with existing methods.
Highlights
The high computational complexity and low reconfigurability of generalized discrete Fourier transform filter banks (GDFT-FBs) render them unfit to handle the upcoming radio standards in software-defined radio (SDR) handsets
Two improvement methods were used for the realization of the algorithm: The first improvement was achieved by hybridizing CD1 and FRM filters with the GDFT
The performance of the method was further improved by using a parallel distributed arithmetic-based residue number system
Summary
The high computational complexity and low reconfigurability of generalized discrete Fourier transform filter banks (GDFT-FBs) render them unfit to handle the upcoming radio standards in software-defined radio (SDR) handsets. The main cause of such high filter order is the huge number of multipliers consumed during the channelization operations. Multipliers contribute remarkably to the complexity of digital filters and channelization algorithms, as evidenced by the high filter orders obtained during implementation. Metrics for the evaluation of the computational load are based on the following scales: Very High, High, and Low. The Very High scale indicates higher filter order and filter coefficients.
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