Improving electrical performance in Ge–Si core–shell nanowire transistor with a new stripped structure

Abstract

A new device structure based on Ge–Si core–shell nanowire is proposed. Owing to the fact that the Si shell is stripped at the source/drain end, the density and electrostatic potential of the holes is gradually distributed in the source/drain region of the new structure, which results in a higher gradient of quasi-Fermi potential in the channel underneath the gate. We observe a higher current ratio for the on-off state and improved output characteristics in the new structure via TCAD simulation. Besides, in the proposed structure we can adjust the on-state current by changing the source/drain length for the same gate length. This provides a feasible approach to optimizing a junctionless nanowire transistor device.