Improvement of Wafer Edge Defect for Finfets Technology

Abstract

In this paper, the formation mechanism and solution methods of wafer edge peeling and silicon (Si) residue defects in Fin loop are studied. The experiment results show that the appearance of wafer edge peeling defect is related to the edge bead removal (EBR) process. The un-optimized EBR not only results in the loss of hard mask oxide at wafer edge, but also lead to form a ring of redundant structures at wafer edge, which are the source of wafer edge peeling defect and further deteriorate in the subsequent process. The peeling defect can be greatly reduced by optimizing EBR condition and wet cleaning process. The formation of wafer edge Si residue defect is mainly attributed to the process dimension deviation and un-cleaned residue of the front layer, which can block subsequent Fin etching process and lead to form Si residue defect. Optimization of EBR condition and enlargement of wafer edge processing size can eliminate the Si residue defect. By improving wafer edge peeling and Si residue defect, the wafer edge yield loss can be reduced by 65%.