Improvement of SOI Trench LDMOS Performance With Double Vertical Metal Field Plate

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In this paper, a novel high-voltage trench lateral double-diffused metal-oxide-semiconductor field effect transistor (TLDMOS) based on silicon-on-insulator technology is proposed. The new structure is characterized by a double vertical metal field plate (DVFP) in the oxide trench, which is surrounded by heavily doped N/P pillars [superjuction (SJ)]. The DVFP introduces five new electric field peaks in the bulk of drift region compared with the conventional TLDMOS, leading to the breakdown voltage (BV) increase. Furthermore, the DVFP and SJ provide an electrons accumulation layer at the interface of the N pillar and oxide trench under the ON-state, reducing the specific ON-resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ). With the 2-D device simulation, a BV of 840 V and a R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> of 60.2 mQ · cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> are realized on a 25-μm-thick SOI layer and 0.5 μm buried oxide layer, and the Baliga's figure of merit [(FOM), FOM = BV <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ] of 11.4 MW/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> is achieved, breaking through the silicon limit.