Abstract

As we all know, when memories are integrated into arrays on a large scale, the phenomenon of current leakage may occur, which leads to array crosstalk. The selection of memristors with self-rectifying effects can be used to solve crosstalk problems without adding additional device cells, allowing for a higher level of array integration under the same conditions. In this article, by optimizing the thickness of the Al2O3 switching layer in the Au/TaO <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{{\text {x}}}$ </tex-math></inline-formula> /Al2O3/TiN self-rectifying memristor (SRM), it is found that the rectification ratio can reach <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim $ </tex-math></inline-formula> 403.79 and the nA level of sneak current can be achieved. The fitting analysis shows that the self-rectification phenomenon related to the thickness of Al2O3 may be related to the effective Schottky barrier between Au/TaO <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{{\text {x}}}$ </tex-math></inline-formula> and TaOx/Al2O3 layers and the tunneling effect with increasing voltage. Under the premise of a 10% read margin (RM), it is calculated that the size of the passive array can reach <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${N}$ </tex-math></inline-formula> = 1425. Changing the thickness of the switching layer in the SRM of the stacked structure can significantly improve the rectification effect, thereby increasing the adaptive scale of the array. Our work provides a feasible path for the subsequent optimization of SRMs, which effectively promotes the development of high-density integrated arrays.

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