Circuit-level simulation of resistive-switching random-access memory cross-point array based on a highly reliable compact model

Abstract

In this study, a simple, reliable, and universal circuit model of bipolar resistive-switching random-access memory (RRAM) is presented for the circuit-level simulation of a high-density cross-point RRAM array. For higher accuracy and reliability, the compact model has been developed to match the measurement data of the fabricated RRAM devices with $$\hbox {SiN}_{{x}}$$ and $$\hbox {HfO}_{{x}}$$ switching layers showing different reset switching behaviors. In the SPICE simulation, the RRAM cross-point array is virtually realized by embedding the empirically modeled memory cells, by which device performances such as read margin and power consumption in the high-density array are closely investigated.