Abstract

This paper depicts the improvement of poly-silicon (poly-Si) holes induced failures during gate oxide integrity (GOI) voltage-ramp (V-Ramp) tests by replacing plasma enhanced oxidation with silicon rich oxidation (SRO), which is cap oxide on transfer gate serving as a hard mask to selectively form salicide. The SRO was found to be capable of completely removing salicide block etching induced poly-Si holes. With this SRO film deposited on poly-gate, the higher density silicon in cap oxide fills the interface of poly-Si grains and repairs the poly-Si film damaged by source–drain (S/D) implantation. The plasma-induced damage (PID) effect is observed and SRO can also suppress this PID effect and, thus, enhance GOI process margin. This is because PID may be enhanced during plasma poly-Si etching and S/D implantation, which induces the under-layer latent defects and deteriorates the adhesion between poly-grains and oxide. The SRO refraction index, which is 1.56 in this study with maximum silane (SiH 4) in cap oxide furnace, was found to play an important role on eliminating poly-holes. In-line SEM inspections show that poly-Si holes happen at open area such as the GOI test patterns of large bulk area and of poly-Si edge. Therefore, in-line defect inspections, which usually check only cell area, fail to find poly-Si holes. Hence, the in-line GOI monitor is proposed to detect such “hidden” defects. In this paper, we found SRO can successfully eliminate poly-Si holes, which lead to GOI failures, with minimum productivity loss and negligible process costs. Since GOI monitor by V-Ramp test is implemented to detect such reliability failure, wafer-level reliability control is recommended to proactively monitor and improve GOI performance. In order to achieve more stringent reliability targets as technology marches to the 0.10 μm era, we introduce the concepts of build-in reliability to facilitate qualifications and to incorporate related/prior reliability concerns for developing advanced processes.

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