Study of silicon-nitride induced damage on thin gate oxide

Abstract

Gate oxide integrity (GOI) is an important reliability test item for silicon process qualification. As devices have scaled down, the thickness of the gate oxide is become thinner. Many researchers have been devoted to GOI test methods, modeling and theory, but physical analysis is still a challenge (Monsieur, F. et al., 2001; Sune, J. et al., 2001; Degraeve, R. et al., 2001). In a standard 0.15 /spl mu/m CMOS process, the nitride silicate layer was enclosed for silicon substrate protection during the subsequent STI etching step. Also, one pad oxide layer was grown before nitride silicate deposition, in order to release the large stress that the nitride layer forces on the silicon substrate. This paper provides a physical failure analysis to help resolve GOI issues in IC process improvement related to silicon-nitride induced damage on gate oxide.