Improvement of Capacitance Equivalent Thickness, Leakage Current, and Interfacial State Density Based on Crystallized High-K Dielectrics/Nitrided Buffer Layer Gate Stacks

Abstract

The gate stack composed of tetragonal/cubic ZrO2 high-K dielectrics and nitrided Al2O3 buffer layer was investigated to reduce the capacitance equivalent thickness (CET), leakage current density (Jg), and interfacial state density (Dit). The high-K tetragonal/cubic phase of ZrO2 was formed by post metallization annealing at a low temperature of 450°C. The Jg was suppressed by the insertion of the Al2O3 buffer layer between ZrO2 and Si. The remote NH3 plasma nitridation on the Al2O3 buffer layer further leads to the deactivation of the oxygen vacancies and the well passivation of the Si dangling bonds. Accordingly, a suppressed Jg of 8.12 × 10−6 A/cm2 and Dit of 2.77 × 1011 cm−2 eV−1 were achieved in the crystallized ZrO2/nitrided Al2O3 gate stack with a low CET of 1.2 nm. The gate stack was also optically probed through the photoluminescence from Si, revealing that the hydrogen passivation and depassivation effects caused by the remote NH3 plasma treatment are highly correlated with the Dit. The results indicate that the crystallized high-K dielectrics/nitrided buffer layer is a promising gate stack structure to improve the electrical characteristics in the advanced metal-oxide-semiconductor devices.