Abstract
In this brief, we propose a data scaling technology (DST) for use in a low-error fixed-width Booth multiplier (FWBM) to reduce truncation errors. The proposed DST reduces the number of redundant bits in the multiplicand, yielding more efficient bits in low-error FWBMs. The truncation errors in FWBMs are reduced by adding a circuit incorporating the proposed DST to them as well as an error-compensation circuit. We found that the signal-to-noise ratio of the proposed DST-FWBM (1 bit) was more than 1.05 dB higher than that of an FWBM without the DST circuit. Long-width DST-FWBMs achieved an accuracy closely approaching the ideal value of a post-truncated multiplier. To verify its performance in a VLSI chip, we implemented the DST-FWBM in a 0.18-μm CMOS process. The proposed DST method was shown to considerably improve the accuracy of FWBMs, rendering this technology suitable for use in digital signal processing techniques.
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