Improved Ti Self-Aligned Silicide Technology Using High Dose Ge Pre-Amorphization for 0.10 µm CMOS and Beyond

Abstract

Improved Ti self-aligned silicide (SALICIDE) technology for 0.1 µm complimentary metal-oxide-semiconductor (CMOS) using high dose pre-amorphization implantation (PAI) is developed. High dose PAI with As and Ge promotes the growth rate of silicidation on polycrystalline silicon gate even when its length is reduced to 0.1 µm. Thus it achieves low sheet resistivity at narrow lines. In addition, the advantage of Ge over As as PAI species is confirmed. Ge PAI does not affect the parasitic resistance increase of p channel metal-oxide-semiconductor field effect transistor (pMOSFET) or junction leakage characteristics because of its electrical neutrality and high solubility in silicon.