Improved thermal stability and hole mobilities in a strained-Si/strained-Si 1− yGe y/strained-Si heterostructure grown on a relaxed Si 1− xGe x buffer

Abstract

A dual channel heterostructure consisting of strained-Si/strained-Si 1− y Ge y on relaxed Si 1− x Ge x ( y > x), provides a platform for fabricating metal-oxide-semiconductor field-effect transistors (MOSFETs) with high hole mobilities ( μ eff) which depend directly on Ge concentration and strain in the strained-Si 1− y Ge y layer. Ge out-diffuses from the strained-Si 1− y Ge y layer into relaxed Si 1− x Ge x during high temperature processing, reducing peak Ge concentration and strain in the strained-Si 1− y Ge y layer and degrades hole μ eff in these dual channel heterostructures. A heterostructure consisting of strained-Si/strained-Si 1− y Ge y /strained-Si, referred to as a trilayer heterostructure, grown on relaxed Si 1− x Ge x has much reduced Ge out-flux from the strained-Si 1− y Ge y layer and retains higher μ eff after thermal processing. Improved hole μ eff over similar dual channel heterostructures is also observed in this heterostructure. This could be a result of preventing the hole wavefunction tunneling into the low μ eff relaxed Si 1− x Ge x layer due to the additional valence band offset provided by the underlying strained-Si layer. A diffusion coefficient has been formulated and implemented in a finite difference scheme for predicting the thermal budget of the strained SiGe heterostructures. It shows that the trilayer heterostructures have superior thermal budgets at higher Ge concentrations. Ring-shaped MOSFETs were fabricated on both platforms and subjected to various processing temperatures in order to compare the extent of μ eff reduction with thermal budget. Hole μ eff enhancements are retained to a much higher extent in a trilayer heterostructure after high temperature processing as compared to a dual channel heterostructure. The improved thermal stability and hole μ eff of a trilayer heterostructure makes it an ideal platform for fabricating high μ eff MOSFETs that can be processed over higher temperatures without significant losses in hole μ eff.