Improved reconfigurability and noise margins in threshold logic gates via back-gate biasing in DG-MOSFETs

Abstract

We present a compact and error tolerant implementation of reconfigurable threshold logic gates (TLG) based on nanoscale DG-MOSFET transistors. The use of independently driven double-gate (IDDG) MOSFETs to build a TLG leads not only to fine-grain reconfigurability by way of voltage-adjustable threshold level (T), but also allows one to vary input weights (w i ) or reduce number of inputs (x i ), depending on the design preferences. Operation of the proposed TLG circuits is verified using UFDG SPICE model, and design trade-offs in terms of size, functionality and performance are also indicated. We show that IDDG MOSFETs lead to more efficient and compact TLG circuits that have better design latitude and noise immunity than the conventional counterparts, while also improving the overall reconfigurability. When the back-gate dynamic threshold adjustment afforded by the ultra-thin (<10 nm) DG-MOSFETs on SOI substrates is properly understood and utilized, similar to the floating-gate logic architectures, it can be effectively harnessed to create reconfigurability beyond T and can simplify TLG circuit design.