Abstract

This work presents the comparative study of three different heterojunction SOI-TFET architectures: conventional SOI-TFET, gate overlapped on source SOI-TFET and oxide overlapped on source SOI-TFET. Gate oxide overlapped on source SOI-TFET reported significant improvement in ON current (18µ A/µm) and Ion/Ioff ratio (1010). In addition to significantly low average subthreshold swing (22 mV / dec), the Miller capacitance is also improved as compared to conventional heterojunction SOI-TFET. The proposed device is optimized using 2D Synopsys TCAD simulation and it reveal that the simple oxide overlap on the germanium-source region increases the tunneling area as well as the tunneling current without degrading the band-to-band tunneling (BTBT) and improves the device performance.

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.