Improved language support for Verilog elaboration in Odin II and FPGA architecture benchmarking in the VTR CAD tool

Abstract

Field-programmable gate arrays (FPGAs) are integrated circuits that can be designed or configured after manufacturing. They are used in many disciplines to create prototypes of hardware or in applications where hardware functionality needs to be changed more frequently. Design of new FPGA architectures requires tools that allow developers to create new structures and test those structures in order to compare the results to already established solutions. Boolean circuits, implemented on the FPGAs are compiled using hardware description languages such as Verilog or VHDL. The VTR (Verilog to Routing) CAD (Computer Aided Design) tool, compiles Verilog source code that targets specific hardware resources as FPGAs and ASICs (Application Specific Integrated Circuits). The VTR CAD tool consists of three tools: Odin II, for elaboration from Verilog to a netlist, ABC, for logic synthesis, and VPR, for physical synthesis and analysis. Odin II currently supports only a sub-set of constructs in Verilog language. This paper describes improved and expanded language support for Verilog elaboration introduced in Odin II, in order to provide developers with a tool set to assist in modern FPGA research. With this enhanced language support, a subsequent evaluation of the performance characteristics of VTR flow with a set of benchmarks that are supported by VTR is performed.