Hard and Soft Logic Trade-offs for Multipliers in VTR

Abstract

This paper discusses improvements to the Verilog- To-Routing (VTR) Computer Aided Design (CAD) tool, that enables synthesis of Verilog circuits to a Field Programmable Gate Array (FPGA) architecture, previously impossible due to device size limitations imposed by device growth. The proposed solution allows reducing device sizes required for well known circuits, through exploring the space/performance trade-off question at a finer granularity at early CAD stages. Results of as much as 2.63 times increase in performance and a 48% reduction in device size have been achieved for some circuits.