Improved Delay Estimation Model for Loop based DSP cores

Abstract

Schedule delay or latency of a control data flow graph (CDFG) is determined during scheduling in design space exploration (DSE) process of high level synthesis (HLS). Estimated delay must be accurate enough otherwise it may mislead the DSE to reach non-optimal solution (violating user constraints). Typically latency of a loop based DSP core is calculated using an approximate delay model by unrolling the loop with different values of loop unrolling factor (UF). However there are limitations in existing delay model due to which latency determined is less accurate than commercial HLS tools such as Vivado HLS. This barrier between existing delay model used during DSE in HLS and Vivado HLS tool has been solved by proposing an improved (accurate) delay estimation model in this paper. This model can be used in conjunction with any commercial HLS tool in case of performing DSE of DSP cores. In this paper we achieve this by evaluating the latency of Vivado HLS tool after synthesizing high level description (C, C++ or system C) of same loop based design by imposing resource constraints and UF as optimization directives. Results indicate that the proposed delay model is able to calculate delay with same accuracy as a commercial HLS tool, which thus enables this model to be integrated seamlessly with any DSE approach during low cost architecture exploration of a loop based DSP core.