Improved DC Performance of Nanotube Junctionless Field-Effect Transistors with Dielectric Pocket Integration

Abstract

In this paper, a nanotube architecture of Junctionless FET (JLFET) is investigated wherein it is observed that the performance characteristics of JLFET are improved by introducing Dielectric Pockets into the device near the source-channel and channel-drain interfaces by coming up with a novel structure of nanotube junctionless FET (NTJLFET) called as Dielectric Pocket-NTJLFET (DP-NTJLFET). Using TCAD tool, the proposed DP-NTJLFET has been simulated for a channel length of 20 nm in order to consider and show the improvement in various short-channel effects. The inclusion of Dielectric Pockets into the device significantly reduced the OFF-state current, which eventually improved the current switching ratio (∼2600%) for a pocket length and thickness of 4 and 7 nm, respectively. Further, the proposed device exhibits an improved subthreshold swing characteristics and a better measure of DIBL (improved by ∼12%) for DP-NTJLFET as compared to the conventional NTJLFET. As a result of achieving low OFF-state current, the proposed DP-NTJLFET may be found suitable for the future low-power applications.