Improved current drivability with back-gate bias for elevated source and drain structured FD-SOI SiGe MOSFET

Abstract

Fully depleted (FD) silicon-on-insulator (SOI) MOSFET structure with back-gate bias is suggested for high speed and low power consumption for portable communication application. Ni silicide is demonstrated for improving current drivability for low power consumption by reducing series resistance in the source and drain region. Threshold voltage adjustment is also achieved through applied back-gate bias. For the formation of the buried back-gate, the selection of impurity type as well as its doping concentration is controlled. Employing back-gate bias for FD-SOI NMOSFET, improved current drivability with variable threshold voltage is achieved. Short channel devices are fabricated and its electrical characteristics are obtained under various conditions.