Improved binary‐weighted split‐capacitive‐array DAC for high‐resolution SAR ADCs

Abstract

An improved split-capacitive-array digital-to-analogue converter (DAC) with an optimised segmentation degree (i.e. the number of bits in the most significant bit (MSB) sub-array) is proposed to reduce the area, the switching power consumption and improve the linearity compared to a conventional binary-weighted (CBW) capacitive-array DAC and a conventional binary-weighted split-capacitive-array with an attenuation capacitor (BWA) DAC. The presented analysis considers the area and the power dissipation from the DAC as well as the analogue-to-digital converter's (ADC's) dynamic performance to determine the optimum segmentation degree for the proposed split-capacitive-array DAC and the BWA DAC. Using the minimum matching requirement for the unit capacitor in a 12-bit CBW DAC, the proposed split-capacitive-array DAC with an MSB:LSB = 8:4 segmentation reduces the input capacitance by 2× and reduces the switching power by 15× compared to the 12-bit CBW DAC. It also improves the ADC's dynamic performance and reduces the switching power by 3.75× compared to the conventional 12-bit BWA DAC with an MSB:LSB = 10:2 segmentation.