Implementation of VLSI Based Efficient Lossless EEG Compression Architecture using Verilog HDL

Abstract

If In reality, electroencephalography signal data transfer through the Wireless Network is a frequently used device related to stability and performance problems. This study, the lossless EEG compression circuit architecture of an efficient VLSI device is suggested to increase both the capability of EEG signal transmission and reliability over WBAN. A new lossless data compression technique consisting of even a proposed neural prediction, a casting a vote solution and a quadra probability compression codec has been applied to the proposed architecture. The mid equilibrium encoder consists of a static coding table of multiple Binary and Areas such as training encoders using the comparator and multiplexer’s fundamental components. Help boost the efficiency of the proposed system; a pipelining method was applied. Produce the suggested specification, a 0.18 m CMOS technology containing 8215 gates under 100 MHz clock speed under an operating environment. To test the usefulness of the suggested compression rate technique, for 25 channels, this results in a mean value of 2.35. This work accomplished a 9.6 %increase in compression rate and a 24.1 % decrease in processing costs relative to new competition equipment lossless EEG compressed designs, although keeping a constant interface simplicity.