Abstract
We present an architecture for the implementation of the radix-4 FFT butterfly with redundant arithmetic, based on the utilization of carry-save adders and a signed-digit representation of the multipliers in the multiplications. As the carry propagation is eliminated, a high throughput is maintained with a reduced hardware cost when compared to other architectures based on carry-propagate additions.
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More From: IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
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