Implementation of self-checking two-level combinational logic on FPGA and CPLD circuits

Abstract

Very large scale integration (VLSI) technology has evolved to a level where large systems, previously implemented as printed circuit boards with discrete components, are integrated into a single integrated circuit (IC). But aggressive new chip design technologies frequently adversely affect chip reliability during functional operation. The use of a concurrent error detection (CED) scheme in order to achieve the high reliability requirement of modern computer systems is becoming an important design technique. The present paper describes implementations of separable codes for CED within VLSI ICs based on VHDL descriptions. Four schemes for concurrent error detection are analyzed: duplication of a combinational logic, Berger codes, Bose-Lin codes, and parity-check codes. Results concerning area overheads and operating speed decreases for 18 circuits, when they are implemented in FPGA and CPLD technologies, are reported.