Implementation of Power Efficient Flash Analogue-to-Digital Converter

Avireni Srinivasulu,Taninki Sai Lakshmi,Pittala Chandra Shaker

doi:10.1155/2014/723053

Abstract

An efficient low power high speed 5-bit 5-GS/s flash analogue-to-digital converter (ADC) is proposed in this paper. The designing of a thermometer code to binary code is one of the exacting issues of low power flash ADC. The embodiment consists of two main blocks, a comparator and a digital encoder. To reduce the metastability and the effect of bubble errors, the thermometer code is converted into the gray code and there after translated to binary code through encoder. The proposed encoder is thus implemented by using differential cascade voltage switch logic (DCVSL) to maintain high speed and low power dissipation. The proposed 5-bit flash ADC is designed using Cadence 180 nm CMOS technology with a supply rail voltage typically ±0.85 V. The simulation results include a total power dissipation of 46.69 mW, integral nonlinearity (INL) value of −0.30 LSB and differential nonlinearity (DNL) value of −0.24 LSB, of the flash ADC.

Highlights

Flash analogue-to-digital converter (ADC) has a high data conversion speed, low resolution, and large chip area along with large power dissipation and is preferred for providing high sampling rates
The Wallace tree adder technique is effective in removing the bubble errors but it is at the cost of speed reduction and increased power dissipation [25]
The advantages of this flash ADC are as follows: power consumption is at minimum, errors in the design are minimized, and the proposed configuration is designed at the high sampling rate 5-GS/s

Summary

Introduction

Flash ADC has a high data conversion speed, low resolution, and large chip area along with large power dissipation and is preferred for providing high sampling rates. The blocks of flash ADCs are resistor string, comparator’s block, and thermometer to gray and gray to binary encoder. It plays an important role especially in optical data recording, magnetic read channel applications, digital communication systems, and so forth that require a high data processing rate and optical communication systems [5,6,7,8,9,10]. The design constraints of conversion speed are defined especially by the comparators used in the design of flash ADC [8]

Methods

Results

Conclusion