Implementation of negative capacitance over SiGe sourced Doping-less Tunnel FET

Abstract

Abstract This paper proposes and investigates the performance of SiGe sourced Doping-less Tunnel Field Effect Transistor (DLTFET) by applying non-hysteretic Negative Capacitance (NC) effect using a ferroelectric material PZT. The parameters of PZT such as thickness (tFE), capacitance (CFE) and voltage (VFE) across the ferroelectric are calculated using the Landau-Khalatnikov equation. The device can operate at a gate voltage of 0.49 V [optimized] with a lowest achieved threshold voltage (VT) ~0.065 V. The average sub-threshold slope (AVSS) was scaled down to ~20 mV/dec and the sub-threshold slope (SS) was reduced to ~ 15.5 mV/dec at PZT thickness (tFE) 1.50 × 10−04 cm without affecting the maximum ON-current and the minimum OFF-current attained by the device. The effect of varying tFE on the simulated results has also been investigated. An intermediate value of tFE i.e. 1.50 × 10−04 cm is proposed to be ideal for the SiGe sourced DLTFET. The performance of the device is also measured by contour properties under the combined effect of reduced gate voltage and varying tFE. From all the simulation results and their study, it is observed that Negative Capacitance based SiGe DLTFET provides a better SS and VT with a significantly low gate voltage making it ideal for a low power-consuming device.