Implementation of Low Power Strategies in a Base-band Chip in 40nm CMOS Technologies

Abstract

Low power dissipation has become the main design concern for these portable devices as mobiles evolving to multi-media mobile terminals. This paper presents the advanced low power strategies, such as dynamic voltage and frequency scaling, power gating, SRAM retention mode, which are successfully applied in a 40nm base-band chip. This chip has about 23 million gates, with the highest operation frequency of 580MHz in high performance use cases, four operation modes, 24 clock domains and 12 power domains. The base band chip was finally fabricated in a 40nm Low-Power 1P6M standard CMOS logical process.