Implementation Of Logic Fault Detection Techniques Using Fpga 1232 Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP) © Copyright: All rights reserved. Retrieval Number: F12110986S319/2019©BEIESP DOI:10.35940/ijeat.F1211.0986S319 Journal Website: www.ijeat.org Fig. 1. Block diagram of Simple Memory System III. LOGIC FAULT DETECTION TECHNIQUES A. Normal Majority Logic (ML) Decoder The fault present in the input can be corrected by

Abstract

The evolution of automation concept in industries and rising significance for digital mode of communication have in turn stresses the need for reliable, efficient and high performance digital system. One of the major problems faced in the digital transmission is the loss of data and hence an effective technique to detect and correct these faults is necessary. Conventionally, various techniques are used for this purpose. Among them, three of the techniques like Plain Majority Logic (ML) Decoder, Syndrome Fault Detector and Plain ML Detector Decoder (MLDD) are analyzed and compared in this paper. The purpose of this comparison is to identify the most suitable methodology based on its capability to track maximum number of faults in minimum number of cycles, with reduced memory read access time. All these logics are simulated using HDL code and analysis is done to implement it in FPGA. The results reveal that Plain MLDD is found to provide better solution for various digital circuits than other techniques.