Implementation of in‐loop filter for HEVC decoder on reconfigurable processor

Abstract

The in-loop filter comprises deblocking filter and sample adaptive offset filter, which is an important module for improving image quality in a high-efficiency video coding (HEVC) decoder. The in-loop filter has a high computational complexity that accounts for ∼20% of the HEVC decoding computing load. Furthermore, it is difficult to implement a high-performing in-loop filter due to its large conditional processing requirement. First, this study presents a novel reconfigurable HEVC in-loop filter implementation on a coarse-grained dynamically reconfigurable processing unit. Next, a repartition scheme is presented that allows the in-loop filter implementation at a coding tree unit along with the other decoding modules in the HEVC decoder, which satisfies requirements of low latency applications. Finally, a hierarchised-pipeline and synchronised-parallel technique is used to improve performance by eliminating data hazards in pipeline techniques and synchronisation problems in parallel techniques. Implementation results show that the presented HEVC in-loop filter performs up to 1920 × 1080@52 frames per second at 250 MHz. The throughput is 67.5 × 9 × more than solutions based on digital signal processor and general-purpose processor, respectively.