Implementation of High Speed and Low Power Hybrid Adder Based Novel Radix 4 Booth Multiplier

Abstract

Low power consumption and smaller area are some of the most important criteria for the fabrication of high performance systems. Optimizing the speed and area of the multiplier is a major design issue. However, area and speed are usually conflicting constraints so that improving speed results mostly in larger area. In this research main aim was to determine the best solution to this problem by comparing radix-4 multiplier using hybrid adder with normal radix-4 booth multiplier. Continuous advances of microelectronic technologies make better use of energy, encode data more effectively, reduce power consumption, etc. Particularly, many of these technologies address low-power consumption to meet the requirements of various portable applications. In these application systems, a multiplier is a fundamental arithmetic unit and widely used in circuits.