Radix-8 Booth Multiplier in Terms of Power and Area Efficient for Application in Field of 2D DWT Architecture

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This work presents a 16-bit proposed Booth multiplier with a modified 2D DWT architecture. The proposed multiplier gives better performance when compared to existing architecture Canonic Sign Digit (CSD) representation and Booth multiplier in parameters like power, area, and delay. In this proposed method, Booth multiplier, there is no need of generating all the partial products, only the necessary product required by the coefficient is sufficient. By this logic required for generation of partial products gets reduced by which area and power is reduced. In existing 2D DWT architecture with CSD multiplier, it consumes extra clock cycles for the operation, and these extra delay elements are removed which enhances the performance. To show the modified 2D DWT architecture is better than the existing architecture comparison is made with existing 2D DWT architecture with CSD multiplier. It is practicable that for performing the execution, the planned structural design takes fewer digit of clock cycles in comparisons of reported architecture as a result, it found better speed. For the need of comparison with effective results the proposed method, CSD, and Booth multiplier, the synthesis outcomes have been performed using Verilog HDL 42in Cadence Genus 90 nm tools. There observed an improvement of 29.01% of CSD and 28.22% of existing Booth multiplier with improvement for Excess Area Delay Product (EADP) in excess area than the proposed method and 26.12% and 34.97% for CSD and Booth multiplier in excess than proposed multiplier.