Implementation of Hardware Architecture for SVPWM With Arbitrary Parameters

Abstract

A novel hardware digital architecture for the Space Vector Pulse Width Modulation technique is proposed. Its features are the reduced hardware resources and the real-time variation of the values of the carrier and switching frequencies, of the phase and of the amplitude of the three-phase output voltages in addition to not require external reference signals or further processors, like Digital Signal Processor. The basic idea is to pre-calculate a set of normalized dwell-time for only one sixth of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\alpha -\beta $ </tex-math></inline-formula> -plane and, then, to reconstruct through our architecture the effective dwell-times and the right inverter configurations by an optimized management of the memory. The architecture is implemented in a Field Programmable Gate Array Cyclone V using the 6% and the 1.01%, respectively, of the Look-Up Tables and of the Flip Flops and the experimental measurements show the goodness of the generated waveforms and the high numbers of degrees of freedom without the demand of Digital Signal Processor or Personal Computer.