Implementation of Field Programmable Gate Array (FPGA) Based Distributed Arithmetic Gated Current Unit to Achieve High ECG Diagnosis Rate

Abstract

Nowadays, the diagnosis of different dreadful diseases are more important to save human livings by using fast growing Machine Learning and Deep Learning frameworks. Many algorithms such as Convolutional Neural Networks (CNN), Long Short Term Memory (LSTM), and Recurrent Neural networks (RNN) are playing the pivotal role in the diseases diagnosis particularly in detecting heart arrhythmias. But integrating these networks in the real time hardware remains to be daunting challenge among the researchers since it requires more hardware components and in-efficient methods of solving the larger datasets. To solve the aforementioned problem, this paper proposes the novel Distributed Arithmetic (DA) based Gated Recurrent Units (GRU) for achieving the better hardware efficiency and high diagnosis rate. GRU is considered to be simplified structure of the LSTM with reduced computational overhead. The paper also implements the Distributed Arithmetic (DA) operation for implementing the GRU’s hardware components to consume the less energy and delay. The extensive experimentation is carried out using ZYNQ-7000 SoC using hardware and software codesign methodology and tested with ECG datasets from UCI respiratory and performance boundaries such as accuracy, precision, recall, specificity, F1-score, power, delay and area are calculated and evaluated. Finally the validation and comparative analysis is done for the proposed framework. The outcomes proves that, the proposed DA based GRU framework provides promising solutions for the disease diagnosis and significantly utilized the resources during the experimentation.