Implementation of Fault Tolerant Features in the In-House Developed 1553B Controller Core

Abstract

Triple modular redundancy (TMR) is a very effective way of mitigating single event upset (SEU), single event transient (SET) and single event latch-Up (SEL) in digital integrated circuits (IC), field programmable gate array (FPGA) and almost every IC that work under cosmic radiations and heavy electromagnetic disturbance. Here in this work, we have implemented fault tolerance features using TMR concept in MIL-STD-1553B, which is a serial data bus, used in avionics, satellites and for on-board data handling (OBDH) subsystems in spacecraft. We have implemented TMR only in the register part of this data bus controller core as we want for optimisation in the overall fabricated circuit area. The registers have been tripled and sent to a majority-voting logic which acts as a decision-making circuit and produces a single output from a given three inputs. Though there are other ways to implement fault tolerance we found that TMR is one of the best and the simplest ways for making a system fault-tolerant. The results of this implementation have been verified and checked using Xilinx ISE design suite 10.3c.