Abstract
This article describes the modelling and implementation of two different variants of direct frequency synthesizer, and evaluation of the performance of the finished design, in terms of memory and speed efficiency. The frequency synthesizer requirement comes from our complex radio transmission system design. The research activity has been focused on finding an optimal balance between simplicity, speed and memory consumption. The modelling was done in MATLAB environment in floating-point and fixed-point arithmetic, and the actual design was implemented and synthesized using the Xilinx ISE suite. The output has been connected to our customized radio front-end built on the Texas Instruments TRF2443 chip. The front-end output signal has been captured and compared with simulation results.
Highlights
With improvements in the performance of FPGA (FieldProgrammable Gate Array) devices, it becomes important to implement the basic radio system parts in a digital domain
Multiple parts of the radio system can be implemented in a single chip, thereby enhancing the overall efficiency in hardware design
The theoretical part of the paper is dedicated to the precise description of the synthesizer transformation into the fixed point arithmetic
Summary
With improvements in the performance of FPGA (FieldProgrammable Gate Array) devices, it becomes important to implement the basic radio system parts in a digital domain. This enhances circuit design simplicity and offers numerous opportunities for the later modification of the entire system into specific real-world scenarios. Multiple parts of the radio system can be implemented in a single chip, thereby enhancing the overall efficiency in hardware design. As a part of complex radio transmission system design, we have implemented a direct quadrature frequency synthesizer in VHDL language for the Xilinx. The practical part describes the implementation of the designed synthesizer circuit structure in VHDL language
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