Implementation of DCT for video compression with reconfigurable technology

Abstract

Describes the implementation of discrete cosine transform (DCT) algorithms for video compression using reconfigurable logic technology. We present two approaches for the implementation of the DCT. We discuss their time and area limits using Xilinx 4010 look-up table (LUT) based field programmable gate array (FPGA). The result shows a 50% area reduction or 2 times throughput improvement if we use distributed arithmetic instead of conventional arithmetic to implement DCT using LUT-based FPGA.