Implementation of Carry Save Adder Using Novel Eighteen Transistor Hybrid Full Adder

Abstract

A novel 1-bit hybrid full adder circuit is implemented using eighteen transistors. Simulations are done using the Cadence Virtuoso Schematic Editor in 180 and 90 nm technologies. The performances are evaluated based on its speed, average power consumption, and power-delay product. The proposed hybrid full adder has low power and energy consumption as compared to other full adder designs. Finally, a four operand, eight-bit carry-save adder with a final carry propagate adder was implemented using the proposed full adder, and its performance is analysed based on its average power consumption in 90 nm technology. This design has low average power consumption compared to CSA implementation using other existing full adder design styles.