Implementation of Braun Multiplier with Efficient Pyramidal Adder Structure for Arithmetic Applications

Abstract

Multiplier plays key role in Signal Processing and VLSI based environment applications, as it consumes more power and area compared other devices. In real time applications power and area are important parameters. Multiplier is essential component as it occupies large area and consumes more power compared to any other element .we have so many adders to design multiplier .In this paper Pyramidal adders are used which uses half-adder and full-adder to increase the speed and to reduce the number of gates used in the multiplier, but delay is not decreased significantly. If we modify the Pyramidal adder with XNOR’s and MUX instead of normal half-adder and full-adder, such pyramidal adder uses less gates and delay is reduced compared normal 16-bit adder. The use of XNOR’s and MUX in Pyramidal adder reduces delay, as the MUX function is only select the output among inputs. The use of such pyramidal adder in multiplier delay can be decreased greatly.