Design and Implementation of Efficient FIR Low Pass Filters Based on Vedic and Traditional Digital Multiplier Algorithm

Abstract

AbstractThe need of portable, compatible and high-speed signal processing devices has increased with the explosive growth in portable multimedia applications. Advancement in the digital world has led to high-speed VLSI digital signal processing. Functions like signal separation and signal restoration done by filter are one of things that is common in most of the DSP functions. Multipliers are the significant components of many signal processing systems viz. finite impulse response (FIR) filters, arduino, ARM processors, digital signal processors, etc. As multiplier is the slowest clement in the system, the system’s computation generally depends on multiplier delay. With a view vocal for local, we have tried to use the findings of Vedic culture used for computation purpose in manuscript (Int J Eng Adv Technol 9:4131–4139 [1]; IET Circ Devices Syst 11:196–200 [2]; Proceedings of 2nd international conference on recent multidisciplinary research (ICRMR-2018). Asian Institute of Technology Conference Centre, Thailand, pp 1–6 [3]; Int J Recent Technol Eng 8:1235–1239 [4]) to design low pass digital finite impulse response filter, using equiripple method of design for selected multiplication algorithm such as Vedic, Array, Dada, Wallace, Sequential and Booth [5, 6] having filter order four, eight, sixteen, thirty two and sixty four and then their comparison on the scale of speed, area, memory usage and level of logics used.KeywordsFIR filterVedicVHDLFilter design and analysis (FDA)